Design and verification of voting machine with Cross voter detection User Verilog

Abstract

This article presents an efficient Verilog-based secure voting machine with cross-voter detection, ensuring election integrity. Designed for multiple candidates and voters, it prevents unauthorized votes through voter ID system. The Verilog module, using flip-flop, stores candidate votes and IDs, implementing cross-voter detection to maintain fairness. Parameterized for scalability, the module supports a configurable number of candidates and voters, featuring a reset option. Optimizing hardware resources, the design prioritizes efficiency and minimizes voting process latency. The Verilog code forms a foundation for a secure, scalable system adaptable to specify requirements, allowing for additional security measures. Rigorous simulation and testing validate its robustness before real-world deployment, advancing digital voting systems in efficiency, and adaptability. Simultaneously the module unit is used to check the cross voter and if it finds any cross-voter face those will be removed and respective votes will treat as invalid votes. Those invalid votes will remove from genuine votes. One critical aspect is the detection of cross-voter interface, where votes are unintentionally or maliciously attributed to the wrong candidate. Verilog, a hardware description language, offers a robust platform for designing and verifying digital circuits. This abstract presents a verification methodology for detecting cross-voter interference in electronic voting systems using verilog