Implementation of Modified OTFS Transmitter using Fully Parallel and Pipelined Architecture with Verilog HDL

Abstract

This abstract presents an innovative enhancement to the Orthogonal Time Frequency Space (OTFS) based wireless transmitter architecture, focusing on increasing the bit size to 1024 bits for input and 16 bits for output. This modification aims to significantly boost the speed and efficiency of the transmitter, leveraging advanced Fast Fourier Transforms (FFTs) and Inverse Fast Fourier Transforms (IFFTs) in a fully parallel and pipelined hardware architecture on the XC7A35TCPG236-1 FPGA. By optimizing the utilization of LUTs, flip-flops, and input-outputs, the design achieves high accuracy and maximum throughput with minimal hardware resources. This study not only advances the capabilities of OTFS transmitters but also contributes to the broader field of digital signal processing, offering a scalable solution for high-speed data transmission in dynamic environments.